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摘要:An off-chip calibration technology for the 6 Bit 30 Gsps time-interleaved ADC is presented in paper. The mismatches errors are calculated by calibration algorithm base on statistical approximation method. Negative feedback is used to reduce the three mismatches(skew, offset and gain mismatch). The off-chip calibration technology is implemented by FPGA.The measured results show that the average ENOB(Effective Number of Bits) is improved by 0.58, and the average SFDR(Spurious-Noise-Free Dynamic Range) is increased by 11.28 dB c.
会议名称:

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

会议时间:

2016-10-25

会议地点:

中国浙江杭州

  • 专辑:

    信息科技

  • 专题:

    无线电电子学

  • 分类号:

    TN792

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