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摘要:Coarse Grained Reconfigurable Architecture(CGRA) is a pro mising platfo rm based on its high performance and low powe r.Effic ient co mpilers have been developed for improving loop mapping perfo rmance using modulo scheduling,and the Dual-Vdd technique is popularly used to reduce power consumption in CGRAs.To achieve the bes t mapping performance and lowest power consumption simu ltaneously,this paper formu lates a joint optimization proble m of performance and power effic iency of CGRAs and proposes a low power optimization approach integrating Dual-Vdd assignment into the loop pipelining mapping.The e xperimental results show that the proposed optimization approach could reduce the power by 22.5% on average without decreasing performance.
会议名称:

2017 IEEE 12th International Conference on ASIC

会议时间:

2017-10-25

会议地点:

中国贵州贵阳

  • 专辑:

    信息科技

  • 专题:

    无线电电子学

  • 分类号:

    TN79

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