A Timing Skew Calibration Scheme in Time-Interleaved ADC
摘要：This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters （TIADCs）. It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square （LMS） loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.
2013 Electronics and Circuits Conference（ECC 2013）